The PEWs microarchitecture: reducing complexity through data-dependence based decentralization

This paper presents a microarchitecture based on exploiting the locality of data dependences for e ciently executing many instructions per cycle. The instruction window is split into multiple hardware units, and the instruction stream is distributed among them in such a way that data dependent instructions are generally allocated to the same unit. The fetch bandwidth of the processor is enhanced by doing control predictions at a level higher than that of branches, which permits fetching a large number of instructions every cycle despite the presence of taken branches in the instruction stream. The microarchitecture also o -loads most of the work involved in instruction distribution decisions to hardware that is not in the critical path of execution. It also uses a novel hardware mechanism to resolve memory references. The paper also presents detailed simulation results, which show the capability of the proposed microarchitecture to achieve high issue rates. A sensitivity study of the microarchitecture shows its issue rate to be steadily increasing as the number of hardware units is increased from 1 to 8.